With the arrival of the Fourth Industrial Revolution, the inevitable consequence of its development is the miniaturization of integrated circuit dimensions. Interconnect materials must possess excellent electrical conductivity and thermal conductivity, as these are crucial for reducing signal transmission delays and preventing chip overheating. The replacement of aluminum interconnects with copper interconnects represents a revolutionary advancement in the post-processing technology of integrated circuits, thus propelling the development of the integrated circuit industry. However, as semiconductor device dimensions continue to decrease, the rapid diffusion of copper atoms towards the silicon interface poses a significant challenge to the advancement of copper metallization. This diffusion phenomenon severely impedes the performance and reliability of integrated circuits. In response to these challenges, researchers have focused on developing effective diffusion barrier layers in copper metallization. These barrier layers play a crucial role in preventing the undesired diffusion of copper atoms into the silicon substrate, thereby ensuring the integrity and stability of the integrated circuits. Moreover, the development of advanced diffusion barrier materials has become imperative to meet the increasing demands for ultra-thin dimensions, low resistivity, and thermal stability in modern semiconductor devices. The diffusion barrier layer should meet the following conditions:The diffusion barrier layer should have a high melting point and maintain good adhesion with both copper and the dielectric layer, so as to ensure that even at elevated temperature, the layer will not crack due to thermal stress; The diffusion barrier layer should exhibit excellent chemical inertness, which means that it should not dissolve into copper nor react with silicon; The diffusion barrier layer should have low resistivity and good thermal conductivity to facilitate efficient electrical and thermal conduction; The diffusion barrier layer should be deposited uniformly and smoothly onto the dielectric layer to ensure consistent performance across the integrated circuit.