| XIONG Zhengquan,DOU Junwen,CHEN Ying,GAO Neng,HUANG Yin,ZHU Minhao,FENG Xue.#$NPAnalysis of Internal Residual Stress for Precision Grinding Process of Ultra-thin Silicon Wafers[J],54(2):161-172 |
| #$NPAnalysis of Internal Residual Stress for Precision Grinding Process of Ultra-thin Silicon Wafers |
| Received:April 25, 2024 Revised:May 16, 2024 |
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| DOI：10.16490/j.cnki.issn.1001-3660.2025.02.013 |
| KeyWord:silicon wafer ultra-thin precision grinding internal residual stress finite element simulation micro-Raman experiment |
| Author | Institution |
| XIONG Zhengquan |
Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu , China |
| DOU Junwen |
Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu , China |
| CHEN Ying |
Center for Flexible Electronics Technology,School of Aerospace Engineering, Tsinghua University, Beijing , China;Institute of Flexible Electronics Technology of THU, Zhejiang Jiaxing , China |
| GAO Neng |
School of Materials & Energy, University of Electronic Science & Technology of China, Chengdu , China |
| HUANG Yin |
Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu , China |
| ZHU Minhao |
Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu , China |
| FENG Xue |
Center for Flexible Electronics Technology,School of Aerospace Engineering, Tsinghua University, Beijing , China;Institute of Flexible Electronics Technology of THU, Zhejiang Jiaxing , China |
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| Abstract: |
| Ultra-thin silicon-based integrated circuits (usually with a thickness ≤50 μm) are crucial for achieving flexibility in high-performance integrated devices and meeting the demands for advanced device packaging. Backside precision grinding is an important technical approach enabling the low-cost, large-scale production of ultra-thin silicon-based integrated circuits. However, as the thickness decreases, the mechanical strength of silicon-based devices, which are intrinsically brittle, decreases substantially, leading to increased challenges in the grinding process. Moreover, when the device thickness approaches or falls below the thickness of the active layer (approximately ~15 μm), defects and internal residual stress generated during grinding can have a significant effect on the performance and yield of ultra-thin devices. Therefore, controlling the defects and internal residual stress during the grinding process is essential for improving the fabrication technology of flexible ultra-thin silicon-based integrated circuits. Existing characterization methods make it difficult to reliably detect internal residual stress without causing damage to the sample. It is critical to conduct a thorough analysis of the internal residual stress generated during the precision grinding of ultra-thin silicon wafers and establish quantitative relationships between process parameters and internal residual stress. In this study, with the focus on precision grinding processes, local finite element models were successfully developed for both the single-grain single-pass and multi-grain multi-pass grinding on the silicon wafer through the geometric kinematic relationship between the grinding wheel and the silicon wafer. In these models, the effect of the grinding wheel feed rate on the grinding process was transformed into the effect of equivalent grinding depth. The effect of process parameters (grinding wheel speed, grinding wheel feed rate and abrasive grain size), number of abrasive grains, and grinding cycles on the surface quality and internal residual stress of silicon wafers was investigated. Self-rotating precision grinding experiments on 12-inch silicon wafers were then carried out to validate the simulation results. The findings showed that the internal residual stress on the surface of the silicon wafer after precision grinding mainly concentrated at a depth of approximately 50 nm and rapidly decreased along the depth direction. Lowering the grinding wheel feed rate and reducing the abrasive grain size effectively reduced internal residual stress and improved surface quality. Based on the simulation results, the surface and internal areas of the silicon wafer after grinding were approximated to be in an analogous biaxial compression stress state. Then, the residual stress measured with a laser confocal micro-Raman spectrometer for grinding wheel feed rates of 0.5, 0.35, and 0.2 μm/s was (−185±33), (−216±25) , and (−283±41) MPa, respectively. The residual stress obtained from the finite element simulation of multi-grain multi-pass grinding was (−127±32), (−171±43), and (−221±55) MPa, showing good agreement between the two methods. Consequently, it can be seen that the developed finite element model of multi-grain multi-pass grinding can effectively predict the internal residual stress of silicon wafers in self-rotating precision grinding by converting the grinding wheel feed rate into equivalent grinding depth. These results provide theoretical guidance for failure analysis of ultra-thin silicon wafers during precision grinding, which is very helpful for the development and optimization of thinning processes for silicon-based integrated circuits. |
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